HN Debrief

Samsung demonstrates 3D stacked FETs with triple nanosheet channels at 42nm

  • Hardware
  • Infrastructure
  • Materials Science

Samsung’s post describes a 3D stacked FET prototype at 42nm that puts multiple nanosheet channels on top of each other, extending today’s gate-all-around transistor work into a more vertical structure. The pitch is straightforward: once shrinking transistors sideways gets too hard, stack the active device itself upward so you keep channel width and drive current in a smaller footprint. This is still a research demonstration, not a production node announcement, but it points at the same broader industry move as backside power delivery, through-silicon vias, and other 3D tricks: wire delay and density are becoming as important as classic transistor scaling.

If you track semiconductors, the interesting signal is not just smaller "nodes" anymore but whether 3D device structures can deliver usable performance without running into thermal and leakage limits. Expect packaging, cooling, materials, and interconnect advances to matter as much as transistor geometry in the next few process generations.

Discussion mood

Impressed but skeptical. People saw the device fabrication itself as extremely sophisticated, while most of the serious discussion centered on heat, leakage, and whether extra density can be converted into usable performance.

Key insights

  1. 01

    Manufacturing precision is the real feat

    Building vertically stacked nanosheet transistors across 300mm wafers means holding absurdly tight tolerances through dozens of process steps. That shifts the story from a nice transistor diagram to a reminder that leading-edge semiconductor manufacturing is still one of the hardest industrial capabilities on earth.

    Treat announcements like this as signals about manufacturing competence, not just design novelty. If you care about long-term chip competitiveness, watch who can repeatedly fabricate structures this complex at wafer scale.

      Attribution:
    • mschuster91 #1
    • amelius #1
  2. 02

    Leakage current may dominate the heat budget

    Leakage current is not a side issue here. It can consume a large share of total chip power, and it gets worse as devices shrink and temperatures rise. The commenter also noted Samsung’s own graph never drives drain current near zero, which suggests the off-state behavior is already part of the tradeoff, not an implementation detail to hand-wave away.

    When evaluating new transistor structures, look past density and headline speed. Ask how well they turn off, because off-state leakage can erase much of the practical gain in high-performance parts.

      Attribution:
    • mota7 #1
  3. 03

    3D logic is really about interconnect delay

    The strongest technical framing was that the industry is moving upward because on-die signal travel is becoming a first-order bottleneck. Shorter connections can cut latency and parasitic effects, and that matters even when transistor switching energy remains the main power cost. In other words, vertical structures are not only about fitting more transistors in. They are also about reducing the time and energy spent moving signals around the chip.

    If you model future chip performance, stop treating transistors and wiring as separate stories. Interconnect is now a core scaling constraint, so architectures that shorten paths can win even before raw device gains show up.

      Attribution:
    • juancn #1
    • ben_w #1
    • saltcured #1
  4. 04

    Cooling and materials now gate the benefit

    Several comments pushed the issue past transistor shape and toward the rest of the stack. Laser cooling was dismissed as irrelevant for mainstream silicon logic in the near term, while alternative substrates and materials like silicon carbide were raised as the kind of change that might be needed if dense 3D logic is to pay off. That makes CFET-style progress look tied to advances in thermal management and materials science, not just lithography.

    Do not expect transistor innovation alone to carry the next decade. Roadmaps that ignore cooling, packaging, and materials substitution will miss where the bottlenecks are moving.

      Attribution:
    • mrandish #1
    • pajko #1

Against the grain

  1. 01

    Dynamic power still dominates many chips

    The heat discussion leaned heavily toward leakage, but this pushback is useful because it narrows the claim. For many designs, especially high-frequency logic, dynamic switching power remains the bigger limiter. That means shorter interconnects and lower capacitance from denser layouts could still buy meaningful gains even if leakage gets worse.

    Segment your expectations by workload and chip class. A transistor structure that looks unattractive for always-on leakage may still be worthwhile in performance-oriented parts where switching power dominates.

      Attribution:
    • IshKebab #1
  2. 02

    No clear path to faster node timelines

    The suggestion that this could pull sub-1nm timelines forward was met with a simple challenge that never got a solid answer. That is a good corrective. A new device architecture does not automatically accelerate the process-node calendar, especially when it introduces more integration complexity and thermal constraints.

    Be careful turning research demos into schedule forecasts. Device novelty is not the same thing as manufacturable node acceleration.

      Attribution:
    • armitron #1
    • guerrilla #1

In plain english

300mm wafers ↩
The standard large silicon discs, 300 millimeters in diameter, used to manufacture advanced semiconductor chips.
3D stacked FET ↩
A field-effect transistor design that stacks active transistor channels vertically to increase density in the same chip area.
42nm ↩
A reported feature scale of this research device, with nm meaning nanometer, or one billionth of a meter.
backside power delivery ↩
A chip design approach that routes power through the back of the wafer to reduce congestion and improve performance on the front side.
CFET ↩
Complementary field-effect transistor, a more advanced 3D transistor concept that vertically stacks different transistor types to save area.
drive current ↩
The amount of current a transistor can deliver when it is turned on, which affects speed and performance.
gate-all-around ↩
A transistor design where the gate surrounds the channel on all sides, improving control and reducing leakage compared with older designs.
leakage current ↩
Unwanted current that flows through a transistor even when it is supposed to be off, wasting power and producing heat.
lithography ↩
The chipmaking process that patterns tiny features onto wafers using light or other radiation.
nanosheet ↩
A very thin semiconductor channel used in advanced transistors, shaped like a flat sheet and surrounded by the gate for better control.
silicon carbide ↩
A semiconductor material with better thermal and electrical properties than plain silicon for some applications.
static power ↩
Power consumed even when a chip is not actively switching, often driven by leakage current.
through-silicon vias ↩
Vertical electrical connections that pass through silicon so stacked chip layers can communicate. Often abbreviated as TSVs.
wire delay ↩
The time lost when signals travel through chip wiring, which becomes a bigger bottleneck as chips get denser and faster.

Reference links

Background and definitions

Related cooling discussion

Materials beyond silicon