IBM posted a press release for a new research-stage chip technology it brands as “sub-1 nanometer” or “7 angstrom.” The company says it uses a vertically stacked “nanostack” architecture to keep scaling logic chips moving forward, and says production could be possible in about five years. The big clarification is that this is not a chip with sub-1 nm horizontal features etched across the die. The visible structures in IBM’s own images are much larger. The “0.7 nm” label is being used as a node name tied to claimed density or performance equivalence, not as a literal physical dimension.
That framing dominated the reaction. People who know the space said this has been true for years across the semiconductor industry. Node names stopped mapping cleanly to gate length long ago, and now act more like rough generation markers. Several comments argued that IBM is simply taking that already-loose naming convention to a more absurd place by using vertical stacking to claim “sub-1 nm” progress. Others pushed back that literal dimensions are no longer the point anyway. What matters in practice is
PPA, meaning
power, performance, and area, plus how much transistor density you can actually deliver.
The more grounded reading is that IBM likely has a legitimate research result, just not the one a casual reader would infer from the headline. Commenters described it as a
PDK and test-structure style announcement from an R&D lab rather than a production process. IBM no longer runs high-volume leading-edge fabs, so the expected path is licensing and technology transfer to manufacturing partners, as it has done before. Albany came up as the center of gravity here, with IBM’s research fab,
ASML’s
High NA EUV work, and public subsidies all part of the commercialization story. The practical conclusion was straightforward: this is worth watching as upstream process R&D, but not as evidence that sub-1 nm chips are about to hit the market or that the industry has solved the physical limits of transistor scaling.