HN Debrief

The Prospects for 128 Bit Processors ( John Mashey SGI 1995)

  • Hardware
  • Infrastructure
  • Security
  • AI

The linked piece is a 1995 exchange about whether processors would move from 64-bit to 128-bit, with the key question being address space rather than wider vector registers. Mashey’s argument was that jumping to 128-bit general-purpose machines would be expensive in die area, routing, and latency, and that vendors would only do it when real workloads demanded more than 64-bit systems could address. That prediction held up. People pointed out that today’s CPUs still do not expose full 64-bit virtual addresses in practice, usually landing around 48 to 57 bits, which tells you how far we still are from exhausting even the current model.

If you are designing systems, assume 64-bit addressing will remain the practical baseline for a long time and solve growth with distribution, not giant shared-memory assumptions. Watch 128-bit work where it changes semantics rather than scale, especially capability hardware and specialized numerical code.

Discussion mood

Mostly impressed that the 1995 analysis aged well. The mood is practical and slightly amused: 64-bit addressing still looks excessive for mainstream machines, horizontal scaling beat giant shared-memory boxes, and the only compelling modern reasons for 128-bit-like values are specialized safety or numerical workloads.

Key insights

  1. 01

    IBM shipped 128-bit pointers early

    IBM’s System/38 line shows that 128-bit pointers were not just a futuristic idea. They were already used in the Technology Independent Machine Interface in 1980, which is a reminder that wide pointers can make sense as part of an abstract execution model long before they make sense as a commodity hardware address width.

    Do not treat pointer width as identical to physical hardware addressing. If you are building runtimes, VMs, or compatibility layers, wider object references can be valuable even when the machine underneath stays 64-bit.

      Attribution:
    • sillywalk #1
  2. 02

    Extra bits are most compelling for capabilities

    The strongest present-day case for 128-bit-like pointers is carrying metadata, not reaching more RAM. CHERI was the concrete example. It uses capability-style pointers with bounds and permissions, and one commenter pushed the same idea toward cryptographically unguessable addresses. That reframes wide pointers as a security and memory safety tool rather than a scale upgrade.

    If you hear renewed interest in wider pointers, check whether the goal is safer access control rather than larger heaps. That has product implications for secure systems, language runtimes, and isolation-heavy platforms.

      Attribution:
    • flohofwoe #1
    • kev009 #1
    • justincormack #1
  3. 03

    Quad precision survives in software niches

    128-bit floating point did not vanish because nobody needs it. It persists where exact rounding and scientific constants demand more headroom than doubles provide. CODATA adjustments were cited as using quadruple precision in FORTRAN, and math library work was called out as another place where quads simplify correctly rounded double functions compared with slower double-double or arbitrary-precision fallbacks.

    If your product depends on numerics people assume are solved, check whether software-emulated quad precision is hiding in the stack. It can be a silent source of latency and portability headaches.

      Attribution:
    • fsh #1
    • AlotOfReading #1
    • glimshe #1

Against the grain

  1. 01

    LLMs revive giant-memory pressure

    The cleanest pushback was that modern LLM serving makes memory central again. Model weights and KV cache can push deployments into multi-terabyte territory, which looks closer to the old big-memory future than web-era software did. Even so, the implication was not that 128-bit processors are finally due. It was that the pressure is absorbed by sharding and multiuser infrastructure instead of a single shared address space.

    AI infrastructure can make old hardware questions relevant again, but usually at the cluster design layer. Expect pressure on interconnects, placement, and memory hierarchies before you expect a change in native pointer width.

      Attribution:
    • dist-epoch #1
    • kalleboo #1
  2. 02

    Mainstream CPUs missed useful 128-bit floats

    A few people argued the disappointing part of the last few decades is not missing 128-bit addressing but missing native quadruple-precision floating point. The case is that some scientific and mathematical workloads would benefit, and modern processors already move data through wide vector paths, so the absence is a product choice about utility and economics, not proof that the hardware idea is absurd.

    If you work in scientific computing or high-end numerical software, do not assume commodity CPU roadmaps match your needs. Plan around software libraries, accelerators, or specialized systems when precision requirements exceed doubles.

      Attribution:
    • Aardwolf #1
    • TheOtherHobbes #1

In plain english

capability ↩
A protected reference that includes both an address and the rights allowed for using it.
CHERI ↩
Capability Hardware Enhanced RISC Instructions, a computer architecture approach that adds bounds and permissions to pointers for stronger memory safety.
CODATA ↩
Committee on Data of the International Science Council, which publishes recommended values for physical constants.
double-double ↩
A software technique that represents a number using two double-precision floating point values to get more precision than one double alone.
FORTRAN ↩
A long-running programming language widely used in scientific and engineering computing.
KV cache ↩
Key-value cache, memory used by transformer models to store intermediate attention data so they can generate tokens faster.
LLM ↩
Large language model, a machine learning system that generates and edits text or code from prompts.

Reference links

Architecture and historical references

  • Emotion Engine
    Mentioned as an example of a past CPU marketed around moving more data, in contrast to building general-purpose 128-bit systems now.
  • Intel 5-level paging
    Used to support the point that some x86 CPUs now expose up to 57 bits of virtual address space rather than the older 48-bit limit.