Pushing the limits of RISC-V emulation

The strongest reaction was that the baseline result was not surprising at all. A lot of people treated roughly one tenth native speed as the long-standing bar for decent unaccelerated emulation, especially when you are translating between active architectures rather than preserving old software at any cost. That reframed the post from “why is this still so slow” to “welcome to the normal physics of the problem.” From there, the useful additions were about where the next gains usually come from. People pointed to copy-and-patch style JITs and older QEMU techniques as the practical middle ground between a tight interpreter and a full dynamic translation backend. Others pulled the conversation outward to the longer history of portable intermediate binaries, noting that load-time or JIT compilation has been tried repeatedly in systems like IBM i, Java, .NET, Oberon slim binaries, and Apple’s old LLVM Bitcode pipeline. The throughline was simple: faster cross-ISA execution is never just a codegen trick. It is a choice about where you want complexity to live, in the emulator, in the runtime, or in the operating system loader.