HN Debrief

A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better"

  • Hardware
  • Open Source
  • Infrastructure
  • Programming

The post is a response to an earlier essay attacking RISC-V on technical grounds. Instead of disputing every ISA complaint, the author reframes the question. In his world, the win is that RISC-V makes it possible to buy or build very cheap microcontrollers, customize cores without asking ARM for permission, and teach students on parts cheap enough to burn out without fear. He ties that to life outside the usual US and European distribution channels, where official vendors, export checks, and courier minimums can turn tiny electronics orders into absurdly expensive purchases.

If you care about embedded products, education, or regional manufacturing, treat RISC-V as a distribution and business-model story as much as a technical one. If you care about laptops, servers, or broadly portable binaries, keep watching ecosystem consolidation and software compatibility, because that is still the bottleneck.

Discussion mood

Mostly positive about the embedded-accessibility argument and the window it opened into non-US constraints, but skeptical of the article’s broader claims. The dominant mood was that RISC-V is clearly valuable in low-cost embedded and education, yet the rebuttal did not really disprove concerns about fragmentation, software portability, or weak current performance in higher-end systems.

Key insights

  1. 01

    Fixed shipping makes chip price matter more

    The author’s follow-up turned a muddled part of the post into the clearest practical point. When distributors impose a $60 floor, buyers have to order deep to justify freight, so a ten-cent MCU versus a one-dollar MCU decides whether a classroom can stock 1000 parts or 100. That changes how people teach, prototype, and tolerate failure. Cheap parts are not just cheaper. They create room to learn by destroying hardware instead of guarding it.

    If you sell hardware into smaller or import-constrained markets, optimize for order economics, not just unit specs. Low fixed-cost experimentation can matter more than headline performance.

      Attribution:
    • armstrongsubero #1
    • kelnos #1
  2. 02

    A free toolchain is the hidden product

    The bigger gain from a common open ISA is not that binaries run everywhere. It is that a chip company can start with GCC, debuggers, assemblers, and the rest of the development stack already in place instead of building or licensing all of that from scratch. That lowers the barrier to making niche silicon and gives users familiar tools on day one.

    When evaluating an architecture, count the software tooling as part of the platform cost. For custom silicon, mature compiler and debugger support can be more valuable than one more instruction-level optimization.

      Attribution:
    • gertop #1
  3. 03

    Performance lag is mostly money and ecosystem

    The more grounded hardware comments cut through both doom and hype. There is no credible sign that RISC-V is permanently barred from high performance. x86 shows that enough engineering can overcome an ugly ISA, and RISC-V is cleaner than x86 in several ways. What holds it back is decades of ecosystem compounding by ARM and x86, plus the cost of building top-tier cores, boards, firmware, operating system support, and optimized software around them.

    Do not mistake today’s benchmark gap for a permanent technical limit. But also do not plan around imminent parity unless you see sustained investment in the full stack, not just core design.

      Attribution:
    • phire #1
    • madushan1000 #1
  4. 04

    Interesting core work is happening below desktops

    A strong hardware-focused comment pointed to real microarchitectural experimentation in projects like Tenstorrent Ascalon, Ventana, NextSilicon, and OpenXiangShan. The details matter because they show RISC-V work is not stuck at hobby-core level. People are trying fetch optimizers, vector implementation tricks, and high-performance out-of-order designs. Much of that work is shipping first in AI accelerators or specialized hardware, not in consumer PCs, which is why the progress is easy to miss if you only watch SBC reviews.

    Watch accelerator and infrastructure silicon for early signs of RISC-V maturity. By the time a polished workstation chip appears, much of the underlying CPU innovation will already have happened elsewhere.

      Attribution:
    • camel-cdr #1
    • phire #1
  5. 05

    Fragmentation helps chip makers and hurts software

    The strongest anti-hype point was not that optional extensions exist, but that they create the same kind of dialect chaos seen in older families like PowerPC. For silicon vendors, that freedom is exactly the attraction. For OS maintainers, binary distributors, and performance engineers, it means more combinations to support, test, and verify. Existing ARM strength is not just ISA design. It is accumulated expertise, validation, and dependable reference implementations.

    If your business ships software to many devices, demand clear target profiles and extension baselines before betting on RISC-V scale. If you build silicon, the same flexibility may be a reason to choose it.

      Attribution:
    • quotemstr #1
    • Geof25 #1
    • camel-cdr #1
  6. 06

    Open licensing matters as much as royalties

    Several comments sharpened a point the post only implied. The value of RISC-V is not merely avoiding ARM fees. It is avoiding permission. If you want to build a weird core, add features ARM would segment into another product line, or create a custom SoC without negotiating with an owner, RISC-V changes who gets to experiment. That is why enthusiasts tolerate rough edges that would be unacceptable in a finished general-purpose platform.

    Separate license cost from governance control when comparing platforms. Vendor permission can be the bigger strategic risk than the check you write.

      Attribution:
    • zephen #1
    • pixelesque #1
    • PunchyHamster #1

Against the grain

  1. 01

    Cheap distribution is not uniquely RISC-V

    The accessibility story gets weaker once you separate open licensing from reseller channels. Commenters noted that AliExpress and LCSC also carry ARM parts, and one cited Cortex-M0 chips that undercut the article’s headline RISC-V pricing. That suggests the author’s strongest examples are partly about WCH’s distribution choices, clones, and Chinese storefront logistics, not about RISC-V alone.

    Before turning one vendor’s availability advantage into an architecture thesis, compare specific part numbers across the same retail channels. The moat may belong to distribution strategy, not ISA choice.

      Attribution:
    • kelnos #1
    • jiqiren #1
    • murderfs #1
    • unfocso #1
  2. 02

    The rebuttal dodges the high-end argument

    A recurring pushback was that the response celebrates MCU success while claiming victory over a critique aimed at laptops, phones, and servers. Current RISC-V SBCs still trail comparable ARM boards badly on single-core speed and efficiency, and even the closer multicore numbers often rely on more cores and more power. That makes the piece persuasive as an embedded manifesto, not as evidence that one ISA cleanly spans everything from ten-cent controllers to serious application processors.

    Match architecture claims to the actual market tier you care about. Success in custom embedded does not automatically translate into a viable desktop or mobile platform.

      Attribution:
    • phire #1
    • whateverboat #1
    • simcop2387 #1
    • amaranth #1
    • kazinator #1
  3. 03

    Some original ISA complaints may be overstated

    One technically detailed comment argued that parts of the earlier anti-RISC-V critique overstate the benefit of ARM conveniences like multi-register save instructions. On small MCUs with narrow buses and no cache, those instructions still cost multiple memory cycles, so they do not erase the underlying work. The comment also proposed alternative interrupt-bank designs and pointed to other weaknesses, like overflow behavior and context-switch support, as more serious than the headline examples.

    Be careful using microcontroller pain points as proof that one ISA is fundamentally broken. The real tradeoffs may sit lower in the pipeline and memory system than the instruction mnemonic suggests.

      Attribution:
    • codedokode #1

In plain english

arm64 ↩
The 64-bit version of the ARM processor architecture widely used in phones, laptops, and servers.
Cortex-M ↩
ARM’s microcontroller-focused CPU family used in many low-power embedded devices.
ISA ↩
Instruction Set Architecture, the low-level interface that defines the machine instructions a CPU understands.
Linux ↩
A widely used open-source operating system kernel that powers servers, embedded devices, and many desktop systems.
MCU ↩
Marvel Cinematic Universe, the long-running shared universe of Marvel superhero films and shows.
MMU ↩
Multi Material Unit, Prusa’s add-on for switching among different filaments during printing.
out-of-order ↩
A CPU design technique where instructions are executed as resources become available rather than strictly in original program order.
RISC-V ↩
An open instruction set architecture for processors that anyone can implement without paying licensing fees.
SBC ↩
Single-board computer, a compact computer built on one board, such as a Raspberry Pi.
SoC ↩
System on a Chip, a design that combines CPU, memory interfaces, and other major components into a single chip.
x86 ↩
A widely used processor architecture from Intel and AMD that underpins most traditional PCs and many servers.

Reference links

Original and archived article links

RISC-V hardware and core references

Policy and ecosystem context

Related technical projects and historical alternatives