HN Debrief

SIMD in the 90s: Programming Intel's Pentium MMX

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The post is a hands-on look at programming Intel’s Pentium MMX, the late-1990s extension that brought SIMD to mainstream x86 by letting one instruction operate on multiple small integers packed into a 64-bit register. It also highlights the architectural compromise that made MMX awkward from day one: those registers were not really new registers at all, but aliases of the x87 floating-point stack. That meant switching between MMX and floating point needed cleanup like EMMS, and it tied a promising vector feature to one of x86’s strangest legacy subsystems.

If you care about low-level performance work, the useful takeaway is not nostalgia for MMX but a clearer mental model of x86’s baggage: register aliasing, compiler quality, and instruction set transitions often matter as much as raw vector width. For modern code, assume SSE2 as the true floor on 64-bit x86 and treat x87 and MMX as legacy corners you only touch for compatibility or very specific hand-tuned code.

Discussion mood

Mostly positive and nostalgic about the technical history, with a strong undercurrent of relief that MMX is gone. People respected the speedups it unlocked for 1990s media code, but the dominant mood was that MMX was awkward, compiler-hostile, and obviously a stopgap once SSE arrived.

Key insights

  1. 01

    EMMS bugs could poison whole calculations

    Cleaning up after MMX was not a minor bookkeeping detail. Forgetting EMMS could leave the aliased x87 stack marked full, so later floating-point work could start producing NaNs and trigger slow microcode handling as those bad values spread. That turns MMX’s register aliasing from a quirky historical footnote into a direct correctness and performance hazard.

    If you ever maintain old x86 assembly or intrinsics code, audit every MMX to x87 transition explicitly. Bugs here are easy to misdiagnose because they can surface later as random floating-point corruption and large slowdowns.

      Attribution:
    • ack_complete #1
  2. 02

    MMX wins depended on hand-tuned media kernels

    The places where MMX paid off were tightly structured integer workloads such as codecs, image transforms, color conversion, and audio processing. Even there, people only got the expected speedups by writing assembly and scheduling around in-order pipelines, short register files, and awkward instruction latencies. Intrinsics support existed, but real-world compiler output was often so poor that it erased much of the benefit.

    When evaluating old SIMD case studies, separate the instruction set from the toolchain. A claimed win may say more about expert handwritten kernels in a narrow loop than about what a normal compiler could deliver to a larger codebase.

      Attribution:
    • ack_complete #1 #2
    • icelusxl #1
  3. 03

    SSE beat MMX by matching emerging workloads

    MMX’s narrow focus on packed small integers left it ill-suited to the workloads that grew fastest, especially 3D graphics and general numeric code. SSE’s floating-point vectors, standard IEEE rounding, and better shuffle and extract operations fit that world much better. That made SSE the real strategic replacement, while SSE2 mostly widened and generalized a direction that SSE had already made inevitable.

    When choosing low-level primitives, pay attention to which workload the ISA was designed around. A feature can benchmark well in one domain and still lose the platform if it mismatches the next dominant software wave.

      Attribution:
    • ack_complete #1
  4. 04

    SSE2 is the practical baseline on x86-64

    For modern 64-bit PC software, the compatibility floor is much higher than many people remember. AMD64 requires SSE and SSE2, so compilers target those instructions for ordinary float and double math instead of x87. Later x86-64 microarchitecture levels add newer vector features, but SSE1 and SSE2 are part of the base contract.

    If you ship 64-bit x86 binaries, assume SSE2 support and simplify your portability story accordingly. Save x87-specific thinking for long double edge cases, legacy code, or archaeology.

      Attribution:
    • Const-me #1
    • theandrewbailey #1
    • VorpalWay #1
  5. 05

    Early SSE hardware was less clean than the ISA looked

    The move from MMX to SSE did not instantly remove all the underlying baggage. Comments note that Katmai-era Pentium III parts hid aliasing between x87, MMX, and XMM state, and that several Pentium III and Pentium M chips still handled some SSE operations over narrower internal datapaths. So the architectural story looked cleaner to programmers before the hardware fully caught up.

    Do not read an ISA manual as a guarantee of uniform implementation cost. On transitional CPUs, the visible programming model can be much tidier than the microarchitectural reality underneath.

      Attribution:
    • theandrewbailey #1
    • ack_complete #1
    • derf_ #1

Against the grain

  1. 01

    MMX adoption was not actually niche

    Claims that MMX was slow to matter miss how heavily it was used in image and video pipelines. IDCT, motion prediction, YUV to RGB conversion, and alpha blending were exactly the kind of hot inner loops that benefited, and those workloads were commercially important well before general-purpose SIMD programming became common.

    If you are looking back at old instruction sets, judge them by the workloads that paid the bills at the time. Broad developer mindshare can lag far behind heavy use inside libraries, drivers, and codecs.

      Attribution:
    • nojokepoke #1
    • ack_complete #1
  2. 02

    GPUs did not make MMX obsolete overnight

    Tying MMX’s decline to the GeForce 256 compresses the timeline too much. Fixed-function GPUs did not yet handle most decoding and non-display image processing, and moving data back from the GPU over AGP was expensive. CPUs still carried a lot of media work for years, which left room for MMX and then SSE in codec-heavy software.

    When a new accelerator appears, map which parts of the pipeline it really offloads. Early hardware transitions often leave a long tail where CPU-side vector code still matters a lot.

      Attribution:
    • justsomehnguy #1 #2
    • ack_complete #1

In plain english

AGP ↩
Accelerated Graphics Port, an older high-speed connection standard for graphics cards before PCI Express.
AMD64 ↩
The 64-bit extension to x86 introduced by AMD, also called x86-64, which became the standard 64-bit PC architecture.
EMMS ↩
A special x86 instruction that clears MMX state so the processor can safely use the x87 floating-point stack again.
IDCT ↩
Inverse Discrete Cosine Transform, a core computation used in many image and video compression formats such as JPEG and MPEG.
IEEE ↩
Institute of Electrical and Electronics Engineers, whose standards include the common floating-point arithmetic rules used by modern CPUs.
MMX ↩
Multimedia Extensions, Intel’s 1990s x86 instruction set extension for packed integer SIMD operations.
RGB ↩
Red, green, and blue, the three color channels most digital cameras use to represent color images.
SIMD ↩
Single instruction, multiple data, a CPU technique that processes many data values with one instruction for faster numeric or text operations.
SSE ↩
Server-Sent Events, a browser-friendly way for a server to stream updates to a client over HTTP.
SSE2 ↩
The second major version of SSE, adding double-precision floating point and broader integer vector support on x86.
x87 ↩
The floating-point unit architecture used in older Intel-compatible processors.
XMM ↩
The 128-bit vector registers introduced with SSE and used by later x86 SIMD extensions.
YUV ↩
A family of color encodings that separates brightness from color information, widely used in video processing.

Reference links

Original story and architecture references

  • Programming Intel Pentium MMX SIMD
    The submitted article explaining Pentium MMX SIMD programming and its historical context.
  • x86-64 microarchitecture levels
    Referenced to explain the baseline and optional SIMD feature sets within modern x86-64 compatibility levels.
  • x86-64
    Linked in comments to clarify that AMD64 adopted SSE and SSE2 as core instructions and expanded the number of XMM registers.

Period examples and cultural references

  • POD (video game)
    Mentioned as an early game that advertised MMX support, illustrating how Intel marketed the technology to consumers.