HN Debrief

Everyone says assembly is untyped—everyone is wrong

  • Programming
  • Compilers
  • Developer Tools
  • Hardware

The post introduces Odin’s inline assembly design, which replaces the usual stringly GCC-style interface with callable asm templates that look more like ordinary language constructs. The core claim is that assembly is not really untyped. Instructions already constrain operand kinds, register classes, widths, immediate ranges, and hidden effects like flag or register clobbers. Odin turns that into compiler data, so inline asm can be parsed, checked, and diagnosed instead of shoved through as opaque text.

If you ship low-level code, the useful idea here is not the slogan about typed assembly. It is treating inline asm as compiler-understood templates with checked register classes, clobbers, and diagnostics, while keeping an escape hatch for the ugly cases production systems always hit.

Discussion mood

Mostly positive about the engineering goal and negative about the framing. People liked replacing opaque GCC-style asm with compiler-checked templates, but many thought the “assembly is typed” claim was overstated and that the simplified syntax will struggle with real-world oddities, architecture-specific forms, and large asm blocks.

Key insights

  1. 01

    CPUID example exposes checker limits

    The CPUID sample looks like exactly the kind of case this system is supposed to catch, yet it appears to leave ECX unconstrained as an input even though some CPUID leaves use both EAX and ECX. That undercuts the pitch unless the checker can distinguish between a register pinned for output and a register that must also be initialized before the instruction runs.

    Test any inline asm checker with instructions that have hidden inputs and outputs, not just obvious operand lists. If the model misses CPUID-style cases, keep a manual review path for low-level code.

      Attribution:
    • amluto #1
    • CBLT #1
    • tialaramex #1 #2
    • tpmoney #1
  2. 02

    Small snippets benefit more than full asm blocks

    Inline asm gets nasty in production when it stops being a single instruction wrapper and starts using assembler directives, instruction definitions the toolchain does not know yet, runtime patching, and explicit mode switching. Once a block saves registers in custom ways or jumps across 16-bit, 32-bit, and 64-bit modes, instruction-level tables stop being enough to infer clobbers or safety.

    Use designs like this for narrow leaf operations and instruction wrappers. For kernel-grade or toolchain-hacking assembly, you still need a raw path that passes text through unchanged.

      Attribution:
    • jcranmer #1
  3. 03

    This is effect typing, not data typing

    The strongest reframing was that Odin is attaching types to instruction signatures and effects, not to the values flowing through the machine. That is still useful. It lets the compiler track accepted operand classes, clobbers, and side effects in the same spirit as effect systems, which is why the design can improve diagnostics even if it does not make registers carry high-level types.

    Explain this kind of feature to your team as checked instruction contracts. That framing is more precise and will set better expectations than claiming the hardware suddenly has a richer data type system.

      Attribution:
    • genxy #1
    • questionableans #1
    • gingerBill #1
    • jkhdigital #1 #2
  4. 04

    Unified syntax helps when you target many ISAs

    The best defense of Odin’s custom syntax was not aesthetics. It was context switching. If you move between x86-64 and AArch64, or mix a lot of inline asm into ordinary code, one normalized syntax reduces avoidable bugs from flipping operand orders, naming rules, and other vendor-specific quirks. The cost is that someone must map that syntax cleanly onto each target ISA, which critics compared to the long-standing pain of Plan 9 assembly.

    If your compiler or language targets multiple architectures, consistency can be worth more than fidelity to any single vendor manual. The price is ongoing maintenance of an accurate lowering layer per ISA.

      Attribution:
    • adrian_b #1
    • pjmlp #1
    • gingerBill #1
    • WalterBright #1
    • inkyoto #1
  5. 05

    Intrinsics protect optimizers better than clever patterns

    Even when a CPU has instructions with semantics beyond the usual C model, compilers often fail to emit them because earlier optimization passes destroy the recognizable pattern. Intrinsics work because they preserve the intended operation in the compiler’s internal representation, so later passes know not to rewrite it away.

    Reach for intrinsics first when the goal is specific instruction selection under optimization. Inline asm is better reserved for cases the compiler cannot represent or where exact encoding control matters.

      Attribution:
    • minipci1321 #1
    • adrian_b #1

Against the grain

  1. 01

    The abstraction may collapse on odd architectures

    Several comments argued that the syntax looks elegant mainly because it is being exercised on mainstream CPUs with relatively familiar conventions. Once you hit AArch64 forms with overloaded mnemonics, vector-length-dependent encodings, packeted or parallel instruction sets like Hexagon or SHARC, or multi-register operand conventions, the clean surface risks turning into special cases or losing information that matters for performance and readability.

    Do not assume a low-friction asm syntax proven on x86-64 and AArch64 will generalize cleanly. Validate it against the weirdest target you intend to support before you bake the model into the language.

      Attribution:
    • AshamedCaptain #1
    • 10000truths #1
    • gingerBill #1
    • camel-cdr #1
    • appyn #1
    • tialaramex #1
  2. 02

    The GCC comparison overstates the pain

    One concrete criticism was that the article attacked `%0` and `%1` operand references as if GCC forces manual counting, when GCC has named operands through `asmSymbolicName`. That does not make GCC pleasant, but it weakens the case when the old system is described less accurately than it deserves.

    If you are selling a new developer tool by comparison, make the old tool’s limitations precise. Overstating the baseline makes sophisticated readers trust the whole pitch less.

      Attribution:
    • gingerBill #1
    • layer8 #1
    • Krssst #1
  3. 03

    Registers are constrained but values stay untyped

    The strongest philosophical objection was that instruction forms do not make assembly typed in the sense most programmers care about. CPUs may enforce that some operations use scalar, floating-point, vector, or mask registers, but the bits themselves still carry no enduring type, and the same register contents can be reinterpreted by the next instruction without any machine-level complaint. That makes the slogan feel like a category slip even if the checker is useful.

    Expect pushback if you market operand constraints as proof that assembly is typed. Lead with stronger checking and better errors, which are easier to defend and easier for users to value.

      Attribution:
    • adrian_b #1
    • IshKebab #1 #2
    • tialaramex #1 #2
    • camel-cdr #1
    • caspper69 #1

In plain english

AArch64
The 64-bit execution mode of the ARM architecture used by modern ARM processors.
CPUID
An x86 instruction that reports processor capabilities and uses specific input and output registers.
EAX
A 32-bit general-purpose register on x86 processors that many instructions use implicitly.
ECX
A 32-bit general-purpose register on x86 processors that some instructions, including some CPUID forms, use implicitly.
GCC
GNU Compiler Collection, a major open-source compiler suite for C, C++, and other languages.
Hexagon
A Qualcomm processor architecture known for packeted instructions and digital signal processing features.
inline asm
Inline assembly, assembly language embedded directly inside a higher-level language like C, Rust, or Odin.
intrinsics
Compiler-provided functions or built-ins that map closely to specific CPU instructions without writing raw assembly.
ISA
Instruction Set Architecture, the low-level interface that defines the machine instructions a CPU understands.
Plan 9 assembly
A family of assembler syntaxes from the Plan 9 system that normalizes some conventions across architectures instead of following vendor manuals.
SHARC
A family of digital signal processors from Analog Devices with unusual instruction and memory behaviors.
x86-64
A widely used 64-bit CPU architecture found in many servers and desktop machines.

Reference links

Inline assembly and language implementations

Typed assembly and tagged hardware